Disaggregation and offloading of parts of applications to the edge has been one of the key aspects for reducing latency and transfer of high quantities of data to the core. Applications such as the ones for AR/XR are very sensitive to latency and may benefit from running closer to the user mainly in a 5GB network. At the same time, we have witnessed a lot of new programmable hardware (switches, FPGAs, smartnics, IPUs) being deployed at the edge which may be used for running certain parts of the applications. This PhD project must then investigate the new set of programmable hardware and try to deploy part of the applications inside such hardware. There are some recent works that started to investigate this area and should be the starting point for the candidate.
Linux, virtualization, Python, computer networks. It is a must if the candidate has some knowledge on programmable hardware such as P4, Tofino and NetFPGA.
Monthly FAPESP scholarship:
First year: R$ 5.520,00
Second to fourth years: R$ 6.810,00
Plus 20% annually for research contingency funds
(Optionally) 1-Year Research Internship Abroad (BEPE) at a partner international institution.
[1] Towards a Fully Disaggregated and Programmable Data Center. APSys ’22: Proceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems.
[2] CLARA – Automated SmartNIC Offloading Insights for Network Functions. SOSP 2021 – Proceedings of the 28th ACM Symposium on Operating Systems Principles.
[3] Offloading distributed applications onto smartnics using ipipe. SIGCOMM 2019 – Proceedings of the 2019 Conference of the ACM Special Interest Group on Data Communication.
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